Ultralytics LAPPD Readout Card

Ultralytics LLC, in conjunction with the University of Hawaii, is developing a PSI DRS4-based readout solution for Incom LAPPD Micro-Channel Plates (MCPs). The light collected by LAPPDs is amplified by two layers of MCPs and deposited on one or more of the 28 anode strips along the lower LAPPD surface. Ultralytics’ readout card utilizes high bandwidth amplifiers coupled to the DRS4 to sample these electrical pulses at each end of the anode strips. A Xilinx Artix-7 FPGA provides reconfigurable triggering capability and control over digitization of the DRS4 samples. The readout card can record 1024 samples on all anode strip ends (28 per side, 56 total) at up to 5 GSPS. Total power dissipation is 6-20 Watts depending on input signal conditioning, not including FPGA.



LAPPD Readout card schematic and layout document.  DOWNLOAD >

LAPPD Readout card schematic and layout document. DOWNLOAD >

● Dual-sided readout for all 28 LAPPD striplines
● 25 cm tall x 24 cm wide, form-factored to an Incom LAPPD
● 0.7 - 5 GSPS digitizing system based on PSI DRS4 chips
TI LMH3401 amplifiers for full 950 MHz DRS4 bandwidth
● 2x TI ADS52J90, 65 MSPS, 14 bit, 32 channel ADCs
● Parallel digitization of all channels at < 40 μs per event
● Reconfigurable triggering using DRS4 Transparent Mode
● Optically isolated gigabit Ethernet readout through SFP+
● Single +5V input for DC power
Xilinx Artix-7 FPGA

PSI DRS4 Waveform Sampling Chips (8)
● 950 MHz Bandwidth
● 1024 Samples per Waveform
● 600 MSPS - 5 GSPS
● 18-33 mW/Ch

TI LMH3401 Amplifiers (56)
● 7 Ghz Amplifiers
● Fully Differentiable
● 28 Amplifiers/Side
● 178-275 mW/Ch

TI ADS52J90 ADCs (2)
● 32 Channels
● 65 MSPS @ 14 bits
● 5 Gb/s JESD or LVDS Interface
● 22 mW/Ch

● Schematic: https://www.ultralytics.com/s/LAPPD-Card-A22-Design.pdf
● Datasheet: https://www.ultralytics.com/s/LAPPD-Card-A22-Datasheet.pdf
● CAD Drawing: https://www.ultralytics.com/s/LAPPD-Card-A22-CAD-Drawing.pdf
● Software/Firmware: https://github.com/kcroker/lappd